Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material

作者：Joshi Bhavana N; Mhaisagar Yogesh S; Mahajan Ashok M^*

来源：Microelectronics Reliability, 2011, 51(5): 953-958.

DOI：10.1016/j.microrel.2011.01.009

A vital parameter interconnect capacitance in the ULSI has been investigated in this paper. The potential and static capacitance under the metal line strip has been determined by solving the Poisson's equation by finite difference method. It has been observed that, the lowering of interconnect width and spacing between the two metal lines affect significantly on coupling capacitance. The total capacitance (C(T)) is dominantly being contribute

• 出版日期2011-5