A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology

作者：Hafez Amr Amin^*; Chen Ming Shuan; Yang Chih Kong Ken

来源：IEEE Journal of Solid-State Circuits, 2015, 50(3): 763-775.

DOI：10.1109/JSSC.2015.2394323

• Frequency divider
• low power
• multiphase sampling
• multiplexer
• quarter rate
• serial link
• serializer
• transmitter

A power-efficient transmitter is proposed using a multiphase serializer, multiphase dividers using injection-locked oscillators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 gate delay are achieved using only nominal devices in a 65 nm CMOS technology. The divider and serializer operate over a wide range of data rates between 32 and 48 Gb/s limited mainly by the operation range of the frequency synthesizer. The transmitter occupies 0.4 mm(2) and consumes 88 mW from a 1.2 V supply which corresponds to 1.8 pJ/bit of power efficiency.

• 出版日期2015-3