All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector

作者：Gu, Junhui^*; Wu, Jianhui; Gu, Danhong; Zhang, Meng; Shi, Longxing

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(4): 760-764.

DOI：10.1109/TVLSI.2011.2111424

• All-digital
• duty cycle corrector (DCC)
• delay unit
• duty cycle
• precharge

A novel all-digital 50% duty cycle corrector (DCC) is proposed in this paper. The DCC features include a delay unit based on precharge logic gates with low delay time and a robust SR latch under process voltage and temperature variations for final edge combination over wide frequency and duty-cycle ranges. The rising edge of the output clock has a constant delay when comparing to the input clock, which makes it easy to cooperate with a delay locked loop. The circuit is fabricated in Chartered 0.18-mu m CMOS process. The acceptable input clock frequency ranges from 400 MHz to 2 GHz. The correcting error is +/- 3.5% at 1 GHz or +/- 1% at 400 MHz.

• 出版日期2012-4
• 单位东南大学