A novel assertion based Methodology to verify mixed signal SOC designs in Digital and Mixed signal verification flow

作者：Mithun Kumar; H V Ravish Aradhya; K N Murlidhara

来源：International Journal of Engineering Science and Technology, 2011.

• Analog checking
• Analog circuit Verification
• Netlist Checkers
• Verilog-A
• Verilog-A Checkers.

This paper describes a method to verify complex analog circuits. The behavioral models of the complex analog circuits are written in VHDL structural style. The VHDL based assertions are written for checking the behavioral models of the complex analog circuits. The assertions were later transformed into Verilog-A checkers for the actual netlist of the complex analog circuits. The netlist is taken from the actual design which then includes the Verilog-A checkers at selected places. These assertions are verified manually after they are actually asserted for specified condition.

• 出版日期2011