A 14.3% PAE parallel class-A and AB 60 GHz CMOS PA

作者:Li Ning*; Matsushita Kota; Okada Kenichi; Matsuzawa Akira
来源:IEICE Electronics Express, 2011, 8(13): 1071-1074.
DOI:10.1587/elex.8.1071

摘要

At 60 GHz, it becomes difficult to achieve a high power added efficiency (PAE) and large output power for CMOS power amplifier (PA). A parallel class-A and AB pseudo Doherty PA is designed in CMOS 65 nm process to obtain a high PAE and large output power. The PA achieves a 9.8-dB gain at 60 GHz. The measured large signal results show that a maximum power added efficiency (PAE) of 14.3% and 12.0% at 1 dB compression point are realized. The chip consumes 45 similar to 58 mW power from a 1.2-V supply voltage. The chip area is 0.6 mm(2) including pads.

  • 出版日期2011-7-10

全文