摘要

Linearity in current-steering digital-to-analog converters (DAC) is mainly governed by the relative amplitude mismatch between the current sources. In this paper, a digitally intensive statistical grouping method is presented. The method is particularly suitable to be applied to large array of elements without prohibitively increasing the system complexity. An offset insensitive measurement method is also proposed to implement the error compensation grouping method with greater accuracy. The digitally assisted error compensation grouping method is implemented on the 7 unary-decoded most significant bits of a segmented 12 bit current steering DAC. The DAC is realized in a 65 nm CMOS process. Through the proposed technique, the unary current source area is reduced significantly and gives rise to an overall DAC active area of 0.29 mm(2) while achieving integral non-linearity of +/- 0.7 LSB, clearly demonstrating an improvement in unary current cells matching. Due to the digitally intensive nature of the proposed architecture, further area saving could be achieved when implemented in smaller gate-length process such as the 45 nm CMOS process.

  • 出版日期2015-5