A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI

作者：Yang Dongsheng; Deng Wei; Narayanan Aravind Tharayil; Wu Rui; Liu Bangan; Okada Kenichi; Matsuzawa Akira

来源：IEICE Electronics Express, 2015, 12(15): 20150531.

DOI：10.1587/elex.12.20150531

• standard cell
• synthesizable PLL
• low power
• low jitter
• small area
• gated edge injection

A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital library and place-and-routed automatically without any manual routing. The proposed PLL has been fabricated in a 28 nm fully depleted silicon on insulator (FDSOI) technology. The measurement results show that this synthesized injection-locked PLL consumes 1.4mW from 1V supply while achieving a figure of merit (FoM) of -235.0 dB with 1.5 ps RMS jitter at 1.6 GHz. This chip occupies only 64 mu m x 64 mu m layout area with the advanced 28 nm FDSOI process. To the best knowledge of the authors, the PLL presented in this paper achieves the smallest area to date.

• 出版日期2015-8-10