A 5-GHz mesh interconnect for a teraflops processor

作者:Hoskote Yatin; Vangal Sriram; Singh Arvind; Borkar Nitin; Borkar Shekhar
来源:IEEE Micro, 2007, 27(5): 51-61.
DOI:10.1109/MM.2007.4378783

摘要

A multicore processor in 65-nm technology with 80 single-precision, floating point cores delivers performance in excess of a teraflops while consuming less than 100 w. A 2d on-die mesh interconnection network operating at 5 ghz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 terabits per second and a per hop fall-through latency of 1 nanosecond.

  • 出版日期2007-10