Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

作者：Junsangsri Pilin; Han Jie; Lombardi Fabrizio^*

来源：Integration, the VLSI Journal, 2016, 52: 156-167.

DOI：10.1016/j.vlsi.2015.09.005

• Nonvolatile SRAM Cell
• Emerging technology
• Programmable Metallization Cell (PMC)
• Single Event Upset (SEU)
• Hybrid memory

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CEO is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.

• 出版日期2016-1
• 单位东北大学