A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

作者：Kim Jong In^*; Sung Ba Ro Saim; Kim Wan; Ryu Seung Tak

来源：IEEE Journal of Solid-State Circuits, 2013, 48(6): 1429-1441.

DOI：10.1109/JSSC.2013.2252516

• Flash ADC
• high-speed comparator
• offset calibration
• time-domain latch interpolation

A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4.1-GS/s operation while consuming 76 mW of total power. This ADC achieves a figure of merit of 0.625 pJ/conversion-step at 4.1 GS/s.

• 出版日期2013-6