A novel 2.4 GHz CMOS dual-modulus prescaler using new implementation of phase-switching technique

作者：Chi BY; Shi BX^*

来源：International Journal of Electronics, 2002, 89(6): 505-515.

DOI：10.1080/00207210210160954

A 2.4 GHz divide-by-128/129 or 64/65 prescaler using a new implementation of the phase-switching technique is presented. The circuit is implemented in a 0.25 mum CMOS process and HSPICE simulation results using BSIM3.1 (level 49) transistor models are presented. The new architecture and the improved SCL D-flipflop circuit simplify the high-frequency part, thus improving its speed, lowering the power consumption and reducing the design complexity. The simulated operating frequency could be up to 2.8 GHz and the power consumption at that frequency is only 11.60 mW with a supply voltage of 2.5 V. The circuit is very robust to variation of the power supply voltage (2.1 V-2.9 V). In view of its excellent performance, the prescaler could be applied to many RF systems.

• 出版日期2002-6
• 单位清华大学