A 28 nm 0.6 V Low Power DSP for Mobile Applications

作者：Ickes Nathan^*; Gammie Gordon; Sinangil Mahmut E; Rithe Rahul; Gu Jie; Wang Alice; Mair Hugh; Datla Satyendra; Rong Bing; Honnavara Prasad Sushma; Ho Lam; Baldwin Greg; Buss Dennis; Chandrakasan Anantha P; Ko Uming

来源：IEEE Journal of Solid-State Circuits, 2012, 47(1): 35-46.

DOI：10.1109/JSSC.2011.2169689

• Low power electronics
• microprocessors

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (V-T) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local variation and achieve a reliable design with minimal pessimism.

• 出版日期2012-1
• 单位MIT