New advances of high-level synthesis for efficient and reliable hardware design

作者：Campbell Keith; Zuo Wei; Chen Deming^*

来源：Integration, the VLSI Journal, 2017, 58: 189-214.

DOI：10.1016/j.vlsi.2016.11.006

• High-level synthesis
• Designer productivity
• Quality of results
• Reliability
• Security
• Verification
• Validation
• Time to market
• Modeling
• Performance
• Low power
• Area cost
• Polyhedral optimization
• Parallel languages
• Interconnect optimization
• Variation aware
• Multicycle path
• IP integration
• Benchmarks

The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniques for dealing with the widening productivity gap, e.g., IP reuse and integration, virtual platform modeling, formal verification and others, high-level synthesis (HLS) has been touted as an important solution as it can significantly reduce the number of man-hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HIS can be inferior compared to that of manual RTL design. In this paper, we will present a set of new techniques developed recently to drastically improve HLS solutions, which not only improve the traditional design metrics such as circuit performance and energy efficiency but also emerging metrics such as hardware security and robustness. We will also discuss how HLS can collaborate with other techniques to provide a holistic design methodology that can enable the delivery of high-quality designs with much less design cost and much faster time-to-market.

• 出版日期2017-6