An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

作者：Zhang, Liang; Li, Dengquan; Zhu, Zhangming^*; Yang, Yintang

来源：Analog Integrated Circuits and Signal Processing, 2015, 83(1): 103-109.

DOI：10.1007/s10470-015-0512-4

• Asynchronous
• SAR ADC
• Split capacitor array
• High speed
• Signal-channel

This paper presents an 8-bit 500-MS/s asynchronous single-channel successive approximation register analog-to-digital converter (SAR ADC). A split capacitor array technique is applied to decrease the digital-to-analog converter (DAC) settling time. Moreover, the design optimizes the logic delay of the SAR controller, resulting in a better match between the internal clock signal and the DAC settling time. The proposed ADC is simulated in SMIC 65 nm 1.2 V CMOS technology. It consumes 2.15 mW and achieves a signal-to-noise-and-distortion ratio of 49.89 dB, translating into a figure-of-merit of 16.9 fJ/conversion-step.

• 出版日期2015-4
• 单位西安电子科技大学