摘要
A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active RC filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 mu W from 1-V supply while the chip area is 420 x 570 mu m(2) including on-chip passive components required for the ALF and the supply regulator.
- 出版日期2013-6