A 4 GHz Continuous-Time Delta Sigma ADC With 70 dB DR and-74 dBFS THD in 125 MHz BW

作者：Bolatkale Muhammed^*; Breems Lucien J; Rutten Robert; Makinwa Kofi A A

来源：IEEE Journal of Solid-State Circuits, 2011, 46(12): 2857-2868.

DOI：10.1109/JSSC.2011.2164963

• Analog-to-digital conversion
• base stations
• CMOS analog integrated circuits
• continuous-time filters
• continuous-time sigma-delta modulation
• delta-sigma modulator
• multi-bit
• oversampling ADCs
• radio receivers
• wireless communication

A 4 GHz third-order continuous-time Delta Sigma ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm(2) including the modulator, clock circuitry and decimation filter.

• 出版日期2011-12