A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

作者：Tu Yo Hao; Liu Jen Chieh^*; Cheng Kuo Hsing; Hsu Chih Hsun

来源：Analog Integrated Circuits and Signal Processing, 2017, 93(1): 157-167.

DOI：10.1007/s10470-017-1005-4

• Synchronous circuit
• I/Q clock signals
• Quadrature phase output
• Low supply voltage

This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.

• 出版日期2017-10
• 单位中央民族大学