A 0.5-V 8-bit 10-Ms/s pipelined ADC in 90-nm CMOS

作者：Shen Junhua^*; Kinget Peter R

来源：IEEE Journal of Solid-State Circuits, 2008, 43(4): 787-795.

DOI：10.1109/JSSC.2008.917470

• analog-to-digital converter (ADC)
• cascaded sampling
• low-voltage operational transconductance amplifier (OTA)
• pipelined ADC
• switch leakage
• ultra-low-voltage analog circuits

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm x 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.

• 出版日期2008-4