A 4-kb low-power SRAM design with negative word-line scheme

作者：Wang, Chua Chin^*; Lee, Ching Li; Lin, Wun Ji

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2007, 54(5): 1069-1076.

DOI：10.1109/TCSI.2006.888767

• leakage current
• negative word-line (NWL)
• power-delay product
• SRAM
• 4-T SRAM cell

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz.

• 出版日期2007-5
• 单位中山大学