摘要

A new burst-mode clock recovery device regenerating the clock at the timing of the first data bit from the input burst-mode packet has been proposed and experimentally demonstrated. The setup of proposed device is composed of simple logic gates and performs successfully regardless of the unstable delay time of feedback loop in the CDR (clock and data recovery) device. After performance evaluation, we have found that the device successfully generates the clock at 155.52 Mb/s and is able to perform clock recovery with a dynamic range of 21 dB at BER = 10(-10).

  • 出版日期2010