摘要

This brief reports a compact and fully integrated three-stage charge-pump (CP) scheme with a 1:10 step-up ratio for energy-harvesting applications. To undertake a low-voltage input (e.g., from thermoelectric or solar source), our CP scheme features a differential bootstrapped ring-VCO generating six-phase clock signals with a boosted swing. Driven by replicas of these swing-boosted clock signals, the entailed number of CP stages is reduced and a 1:10 step-up ratio can be achieved with only a 3-stage CP, resulting in a higher PCE. Using the replicas of the clock signals also reduces substantially the dependency of the clock frequency on the load drivability. Fabricated in 65-nm CMOS, a 0.87-V output voltage is measured at a 38.8% power conversion efficiency, under a 500-k Omega load and a 0.15-V input. The chip area is 0.032 mm(2).

  • 出版日期2018-2
  • 单位澳门大学