A K a-Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

作者：Chang Shuo Hsuan; Chen Chun Nien; Wang Huei^*

来源：IEEE Microwave and Wireless Components Letters, 2018, 28(8): 708-710.

DOI：10.1109/LMWC.2018.2844345

• CMOS
• power amplifier
• switched capacitor

In this letter, a Ka-band dual-mode power amplifier with a new topology is fabricated in 65-nm standard CMOS. The PA with the switched capacitor to modulate the output impedance to match the optimal load impedance of the operation mode provides efficiency enhancement in low-output power region and costs smaller chip size. The PA demonstrates 19.9 dBm (17 dBm) P-sat, 25.8% (22.8%) PAE(max), 17 dBm (14 dBm) OP1dB, and 14.5% (17.4%) PAE(1dB) at 34 GHz in the high-power (low-power) mode. The total chip size of the dual-mode PA is only 0365 mm(2), including pads.

• 出版日期2018-8