A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

作者：De Caro Davide^*; Romani Carlo Alberto; Petra Nicola; Strollo Antonio Giuseppe Maria; Parrella Claudio

来源：IEEE Journal of Solid-State Circuits, 2010, 45(5): 1048-1060.

DOI：10.1109/JSSC.2010.2043461

• Clock synthesis
• digitally controlled delay line
• EMI reduction
• spread-spectrum clock generator (SSCG)

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile.
We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations.
A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.

• 出版日期2010-5