BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

作者：Ando Kota; Ueyoshi Kodai; Orimo Kentaro; Yonekawa Haruyoshi; Sato Shimpei; Nakahara Hiroki; Takamaeda Yamazaki Shinya; Ikebe Masayuki; Asai Tetsuya; Kuroda Tadahiro; Motomura Masato

来源：IEEE Journal of Solid-State Circuits, 2018, 53(4): 983-994.

DOI：10.1109/JSSC.2017.2778702

• Binary neural networks
• in-memory processing
• near-memory processing
• neural networks
• reconfigurable array
• ternary neural networks

A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically. The prototype chip is fabricated, and it achieves 1.4 TOPS (tera operations per second) peak performance with 0.6-W power consumption at 400-MHz clock. The application examination is also conducted.

• 出版日期2018-4