Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

作者：Jo Manhwee; Lee Dongwook; Han Kyuseung; Choi Kiyoung^*

来源：Integration, the VLSI Journal, 2014, 47(2): 232-241.

DOI：10.1016/j.vlsi.2013.08.003

• Coarse-grained reconfigurable architecture
• Floating-point operations

With a huge increase in demand for various kinds of compute-intensive applications in electronic systems, researchers have focused on coarse-grained reconfigurable architectures because of their advantages: high performance and flexibility. This paper presents FloRA, a coarse-grained reconfigurable architecture with floating-point support. A two-dimensional array of integer processing elements in FloRA is configured at run-time to perform floating-point operations as well as integer operations. Fabricated using 130 nm process, the total area overhead due to additional hardware for floating-point operations is about 7.4% compared to the previous architecture which does not support floating-point operations. The fabricated chip runs at 125 MHz clock frequency and 1.2 V power supply. Experiments show 11.6 x speedup on average compared to ARM9 with a vector-floating-point unit for integer-only benchmark programs as well as programs containing floating-point operations. Compared with other similar approaches including XPP and Butter, the proposed architecture shows much higher performance for integer applications, while maintaining about half the performance of Butter for floating-point applications.

• 出版日期2014-3