A 5.83 pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65 nm CMOS

作者：Zhao Xiongxin^*; Chen Zhixiang; Peng Xiao; Zhou Dajiang; Goto Satoshi

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2013, E96A(12): 2623-2632.

DOI：10.1587/transfun.E96.A.2623

• WiMAX
• bit-serial
• fully-parallel
• layered scheduling
• performance aware
• advanced dynamic quantization
• quasi-cyclic
• low-density parity-check codes

In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. By taking the advantages of both layered scheduling and fully-parallel architecture, the decoder can fully support multi-mode decoding specified in WiMAX with the parallelism much higher than commonly used partial-parallel layered LDPC decoder architecture. 6-bit quantized messages are split into bit-serial style and 2 bit-width serial processing lines work concurrently so that only 3 cycles are required to decode one layer. As a result, 12 similar to 24 cycles are enough to process one iteration for all the code-rates specified in WiMAX. Compared to our previous bit-serial decoder, it doubles the parallelism and solves the message saturation problem of the bit-serial arithmetic, with minor gate count increase. Power synthesis result shows that the proposed decoder achieves 5.83 pJ/bit/iteration energy efficiency which is 46.8% improvement compared to state-of-the-art work. Furthermore, an advanced dynamic quantization (ADQ) technique is proposed to enhance the error-correcting performance in layered decoder architecture. With about 2% area overhead, 6-bit ADQ can achieve the error-correcting performance close to 7-bit fixed quantization with improved error floor performance.

• 出版日期2013-12