A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR Core Based on Wide-Pulsed-Latch Pipelines

作者：Jin, Wei^*; Kim, Seongjong; He, Weifeng; Mao, Zhigang; Seok, Mingoo

来源：IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016-11-07 To 2016-11-09.

DOI：10.1109/ASSCC.2016.7844152

• near/sub-threshold
• pulsed-latch
• pulse width
• time-borrowing
• FIR
• energy-efficiency

This paper presents a significant technique to use wide-pulsed-latches to increase the time-borrowing capability and tolerance of variations in near/sub-threshold (V-t) pipelines. Specifically, we use multi-V-t cells to pad the short paths to extend the pulse width up to one third of cycle time while causing minimal overhead in area and power. Moreover, a simpler pulse/clock distribution network design for pulsed-latch based pipelines is proposed. Compared with traditional pulsed-latch based circuits, our technique achieves over 3X higher time to borrow while decreases the complexity of the clock network effectively. The technique is applied to the design of a 0.35V FIR filter in a 65nm, which achieves 45.2% and 11% improvements in performance and energy efficiency than the flip-flop based implementation, respectively. The measurement results also confirm the robustness of our proposed technique across process, voltage, and temperature variations.

• 出版日期2016
• 单位上海交通大学