Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

作者：Xu Hu^*; Pavlidis Vasilis F; Tang Xifan; Burleson Wayne; De Micheli Giovanni

来源：IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(12): 2226-2239.

DOI：10.1109/TVLSI.2012.2230035

• 3-D ICs
• clock jitter
• clock skew
• clock tree
• power supply noise
• process variations
• skitter

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown to be underestimated up to 36% if process variations and dynamic power supply noise are considered separately, which highlights the importance of this unified treatment. Potential scenarios of supply noise in 3-D integrated circuits (ICs) are investigated. 3-D circuits generated from industrial benchmarks are simulated to show the skitter under these scenarios. The mean and standard deviation of skitter can vary up to 60% and 51%, respectively, due to the different amplitudes and phases of supply noise. The tradeoff between skitter and the power consumed by clock trees is also shown. A set of guidelines are presented to decrease skitter in 3-D ICs. By applying these guidelines to industrial benchmarks, simulations show a decrease in the mean skitter up to 31%.

• 出版日期2013-12