A new parallel hardware architecture for high-performance stereo matching calculation

作者：Seo Young Ho; Yoo Ji Sang; Kim Dong Wook^*

来源：Integration, the VLSI Journal, 2015, 51: 81-91.

DOI：10.1016/j.vlsi.2015.06.005

• Stereo vision
• Stereo matching
• Architecture
• Disparity
• FPGA
• Memory bandwidth

In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time. After analyzing the arithmetic characteristic of stereo matching, we propose a new calculating method that reuses the intermediate results to minimize the calculation load and memory access. From this, we propose a stereo matching calculation cell and a new H/W architecture. Finally, we propose a new stereo matching processor. The implemented H/W can operate at the clock frequency of 250 MHz at least in the FPGA (field programmable gate array) environment and produce about 120 disparity images per second for HD stereo images.

• 出版日期2015-9