A 0.004-mm(2) portable multiphase clock generator tile for 1.2-GHz RISC microprocessor

作者：Jung Inhwa^*; Jung Gunok; Song Janghoon; Kim Moo Young; Park Junyoung; Park Sung Bae; Kim Chulwoo

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2008, 55(2): 116-120.

DOI：10.1109/TCSII.2007.910798

• digital clock generator
• fast lock time
• low power
• low jitter

Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-mu m and in a 0.13-mu m CMOS technologies. They consist of a full-digital CMOS circuit,design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-mu m CMOS technology occupies only 0.004mm(2) and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a +/- 2% phase error having one-cycle lock time.

• 出版日期2008-2