AN EMBEDDED SYSTEM ARCHITECTURE OF AUTOMATIC CENSORED ORDERED STATISTIC DETECTOR TECHNIQUES

作者：Djemal Ridha^*

来源：Journal of Circuits, Systems, and Computers, 2013, 22(7): 1350051.

DOI：10.1142/S0218126613500515

• FPGA
• embedded system
• CFAR
• VHDL-RTL

We designed and tested a novel field-programmable gate array (FPGA)-based embedded system that uses automatic censored ordered statistics detector (ACOSD) algorithms to detect targets in clutter with lognormal distribution. The detection process operates through two techniques called backward and forward ACOSD (B-ACOSD and F-ACOSD, respectively), which work in parallel to increase the detection accuracy and reduce the false alarm rate. Two architectures were considered for the proposed detector. The B-ACOSD algorithm operates the censoring beginning from the last cell belonging to a window of N range cells, whereas the F-ACOSD algorithm considers the censoring based on a scan beginning with the first cell in the same sorted window of cells. The detector is implemented on a FPGA-Altera Stratix II as a system-on-chip that integrates a Nios II core processor with our proposed detector as a co-processor and additional embedded memories and interfaces using parallelism and pipelining. For a reference window of 16 cells, the processor works properly with a processing speed of up to 129.13 MHz and a processing time of only 0.23 mu s, within the range of the maximum tolerated delay of 0.5 mu s fixed by the pulse width [A. Farina, A. Russo and F. A. Studer, IEE Proc. F Commun. Radar Signal Process. 133 (1986) 39-54] for viewing a target at high resolution.

• 出版日期2013-8