科研之友
微信
新浪微博
Facebook
分享链接
摘要
We have proposed a 2 GHz CMOS DifferentialLow Noise Amplifier (LNA) for wireless receiver system.The LNA is fabricated with the 0.18 米m standard CMOSprocess. Cadence design tool Spectre_RF is used to designand simulation based on resistors, inductors, capacitorsand transistors. Power constrained methodology is usedfor the design of Differential Low Noise Amplifier.Consuming 9mA current at 1.8V supply voltage, theproposed LNA exhibits a power gain of 15.87 dB, noiseFigure (NF) of 2.4 dB, S11 of -9.842 dB and S12 of -42.86dB.The input IP3 (IIP3) at 2 GHz is -2.86127 dBm, andconsumes 16.2 mW of power.
- 出版日期2012
