An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

作者：Hu Boyu^*; Ren Fengbo; Chen Zuow Zun; Jiang Xicheng; Chang Mau Chung Frank

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(10): 934-938.

DOI：10.1109/TCSII.2016.2538378

• ADC
• compressive sensing (CS)
• SAR-binary-search (BS)
• self-timed pipeline

This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.

• 出版日期2016-10