A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

作者：Yang, Yixiong; Shi, Xin; Su, Fang; Wang, Zhibo; Yang, Pei; Yang, Huazhong; Liu, Yongpan^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66(5): 1970-1980.

DOI：10.1109/TCSI.2018.2872069

• Direct digital frequency synthesizer (DDFS)
• lookup-table
• rotation
• configurable
• tree-structure
• partition

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)-rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS.

• 出版日期2019-5
• 单位清华大学