A 1.78-3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

作者：Huang Fuqing^*; Wu Jianhui; Ji Xincun; Wang Zixuan; Zhang Meng

来源：Analog Integrated Circuits and Signal Processing, 2012, 72(1): 97-109.

DOI：10.1007/s10470-012-9842-7

• Broadband fractional-N frequency synthesizer
• Sigma-Delta modulation
• Low power multi-modulus divider
• Wideband voltage controlled oscillator

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4 GHz broadband fractional-N frequency synthesizer based on I -I" pound modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The "mod" signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18 mu m RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05 GHz, with phase noise smaller than -85 dBc/Hz at 100 kHz offset, and smaller than -115 dBc/Hz at 3 MHz offset. Its power consumption is only 9.2 mW under 1.8 V supply voltage, and the chip occupies an area of 1.2 mm x 1.3 mm.

• 出版日期2012-7
• 单位东南大学