Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

作者：Lee Shuenn Yuh^*; Chen Chih Yuan; Hong Jia Hua; Chang Rong Guey; Lin Mark Po Hung

来源：Microelectronics Journal, 2011, 42(2): 347-357.

DOI：10.1016/j.mejo.2010.11.004

• Sigma-delta modulator
• Automated synthesis
• Behavioral modeling
• Geometric programming
• Transistor sizing
• Op-amp synthesis

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in 0.35 mu m technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20 KHz estimated by the proposed synthesis tool is 94.19 dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03 dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256 KHz is 59.52 dB, and the HSPICE simulation result is 55.39 dB.

• 出版日期2011-2