A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems

作者：Laflamme Mayer Nicolas^*; Blaquiere Yves; Savaria Yvon; Sawan Mohamad

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61(11): 3135-3144.

DOI：10.1109/TCSI.2014.2334911

• Configurable
• I/O
• LDO
• multi-power rail
• NanoPad
• voltage regulator
• WaferIC
• wafer-scale

We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on its surface. The proposed multi-power-rail pad minimizes power losses and heat dissipation within the circuit. The pad that is fed from two distinct voltage sources providing power at 1.8 and 3.3 V has been implemented and tested. This pad has two merged configurable control loops that can select the power source. Merging takes place through shared transistors. This dual supply pad embeds a voltage regulator that achieves a fast response time of 21.1 ns and that can operate over a wide range of configurable regulated output voltage, from 500 mV up to 2.955 V. This regulator is capable of providing a maximum output current of 40 mA while needing only a very small quiescent current of 126 mu A. The regulator's power supply noise rejection ranges from -25 down to -40 dB for frequencies ranging from 1 kHz up to 1 MHz. The embedded digital I/O pad shares a common output with the power distribution and can be configured from 0.5 up to 3.3 V for a maximum speed of 250 MHz.

• 出版日期2014-11