Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies

作者：Alioto Massimo^*; Consoli Elio; Palumbo Gaetano

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(5): 725-736.

DOI：10.1109/TVLSI.2010.2041376

• Clocking
• energy-delay tradeoff
• energy efficiency
• flip-flops (FFs)
• high speed
• interconnects
• leakage
• Logical Effort
• low power
• nanometer technologies
• VLSI

In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.

• 出版日期2011-5