A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications

作者：Baek Seungjun; Ahn Hyunjin; Nam Ilku; Hur Joonhoi; Yoon Youngchang; Lee Ockgoo^*

来源：IEICE Electronics Express, 2018, 15(9): 20180336.

DOI：10.1587/elex.15.20180336

• CMOS
• adaptive bias
• cascode
• WLAN
• power amplifier
• parallel-combined transistors

This paper presents a fully integrated power amplifier (PA) using parallel-combined transistors with a cascode adaptive biasing, implemented in a standard 65 nm CMOS process. The parallel-combined transistors in the common-source stage linearizes the effective gm. In addition, adaptive bias circuits are applied to both the common-source and common-gate stages to provide optimum operation conditions to each transistor, according to the output power variations. When the fully integrated PA was tested with a modulation and coding scheme 7 (MCS7) 802.11n signal, it meets a -28 dB error vector magnitude and spectral mask requirements at 18.4dBm of average output power, with a power-added efficiency of 13.1%.

• 出版日期2018-5-10