A 25 Gb/s 5.8 mW CMOS Equalizer

作者:Jung Jun Won*; Razavi Behzad
来源:IEEE Journal of Solid-State Circuits, 2015, 50(2): 515-526.
DOI:10.1109/JSSC.2014.2364271

摘要

Low-power equalization remains in high demand for wireline receivers operating at tens of gigabits per second in copper media. This paper presents a design incorporating a continuoustime linear equalizer and a two-tap half-rate/quarter-rate decision-feedback equalizer that exploits charge steering techniques to reduce the power consumption. Realized in 45 nm technology, the prototype draws 5.8 mW from a 1 V supply and compensates for 24 dB of loss with BER < 10(-12).

  • 出版日期2015-2