A Complementary Metal Oxide Semiconductor Process-Compatible Ferroelectric Tunnel Junction

作者：Ambriz Vargas Fabian^*; Kolhatkar Gitanjali; Broyer Maxime; Hadj Youssef Azza; Nouar Rafik; Sarkissian Andranik; Thomas Reji; Gomez Yanez Carlos; Gauthier Marc A; Ruediger Andreas^*

来源：ACS Applied Materials & Interfaces, 2017, 9(15): 13262-13268.

DOI：10.1021/acsami.6b16173

• ferroelectric tunnel junctions
• CMOS process
• nanoscale characterization
• tunneling electroresistance effect
• electronic band alignment

In recent years, experimental demonstration of ferroelectric tunnel junctions (FTJ) based on perovskite tunnel barriers has been reported. However, integrating these perovskite materials into conventional silicon memory technology remains challenging due to their lack of compatibility with the complementary metal oxide semiconductor process (CMOS). This communication reports the fabrication of an FTJ based on a CMOS-compatible tunnel barrier Hf0.5Zr0.5O2 (6 unit cells thick) on an equally CMOS-compatible TiN electrode. Analysis of the FTJ by grazing angle incidence X-ray diffraction confirmed the formation of the noncentrosymmetric orthorhombic phase (Pbc2(1), ferroelectric phase). The FTJ characterization is followed by the reconstruction of the electrostatic potential profile in the as-grown TiN/Hf0.5Zr0.5O2/Pt heterostructure. A direct tunneling current model across a trapezoidal barrier was used to correlate the electronic and electrical properties of our FTJ devices. The good agreement between the experimental and theoretical model attests to the tunneling electroresistance effect (TER) in our FTJ device. A TER ratio of similar to 15 was calculated for the present FTJ device at low read voltage (+0.2 V). This study suggests that Hf0.5Zr0.5O2 is a promising candidate for integration into conventional Si memory technology.

• 出版日期2017-4-19