A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

作者：Reyes Benjamin T^*; Paulina German; Sanchez Raul; Mandolesi Pablo S; Hueda Mario R

来源：Analog Integrated Circuits and Signal Processing, 2015, 85(1): 3-16.

DOI：10.1007/s10470-015-0578-z

• Time-interleaved ADC
• Asynchronous SAR
• Optical receivers
• Calibration
• Fixed pattern noise
• Sampling time error

A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 m CMOS process. The architecture uses 8 time-interleaved track-and-hold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to 25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

• 出版日期2015-10