Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

作者：Entrena Luis^*; Lindoso Almudena; Garcia Valderas Mario; Portela Marta; Lopez Ongil Celia

来源：IEEE Transactions on Nuclear Science, 2011, 58(3): 1078-1085.

DOI：10.1109/TNS.2010.2096433

• Fault injection
• FPGA
• single event transient
• soft error

In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.

• 出版日期2011-6