A 12 bit 250 MS/s 28 mW+70 dB SFDR non-50% RZ DAC in 0.11 mu m CMOS using controllable RZ window for wireless SoC integration

作者：Kim Seonggeon; Kang Jaehyun; Lee Minjae^*

来源：Microelectronics Journal, 2016, 56: 46-56.

DOI：10.1016/j.mejo.2016.08.005

• Digital-to-analog converter (DAC)
• Dynamic-element matching (DEM)
• Return-to-zero (RZ)
• Spurious-free dynamic range (SFDR)
• Signal-to-noise ratio (SNR)
• Noise spectral density (NSD)

A 12-bit current-steering digital-to-analog converter (DAC) in 0.11 mu m CMOS technology is presented for one DAC with a flexible swing and common-mode voltage for both an IQ baseband wireless transmitter (TX) and an envelope tracking (ET) power amplifier that require low power consumption. :The conventional half clock period return-to-zero (RZ) effectively eliminates the code-dependent transient but results in amplitude loss and larger DAC images. The proposed RZ flip-flop generates a controllable RZ signal with a clock duty cycle that is less than 50%, which mitigates such a signal power loss and relaxes the image filtering requirement. In addition, this DAC can easily switch between non-return-to-zero (NRZ) mode and RZ mode to serve various applications. The implemented DAC is character-ized at the sample frequency of 250 MHz and it achieves a spurious-free dynamic range (SFDR) greater than 70 dB up to the Nyquist frequency. The core area of the DAC is 0.117 mm(2) and it dissipates about 28 mW under a 2.5 V supply.

• 出版日期2016-10