A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 mu m CMOS

作者：Park Dongmin^*; Cho SeongHwan

来源：IEEE Journal of Solid-State Circuits, 2012, 47(12): 2989-2998.

DOI：10.1109/JSSC.2012.2217856

• Bang-bang
• dual-pulse ring oscillator
• fractional-N
• frequency synthesizer
• low-noise
• PLL
• reference injection

In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a Delta Sigma fractional-N PLL to generate 2.55-to-3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dual-pulse ring oscillator is employed. Quantization noise from the delta-sigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractional-N PLL. Prototype implemented in 0.13 mu m CMOS process achieves the worst-case RMS jitter of 356 fs(rms) over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worst-case fractional spur measured over 7 different chips is -53.9 dBc and the reference spur is -84 dBc.

• 出版日期2012-12