A processor-independent trace co-processor synthesis method

作者：Sang Sheng Tian; Qiu Shan Qin; Li Xiao Ming^*; Yu Ming Yan

来源：Acta Electronica Sinica, 2011, 39(2): 402-407.

• Co-processors
• Control data flow graphs
• Cyclic structures
• Extraction method
• Hardware and software
• Hit rate
• HW/SW partitioning
• Intermediate representations
• Machine instructions
• Processor architectures
• Speculative execution
• System level design
• Trace

The architecture-independent hot trace extraction method is presented, with which the processor architecture-independent trace co-processor synthesis is achieved by promoting trace-based HW/SW partitioning from the level of machine instruction to that of control data flow graph of intermediate code. To support trace predication in cyclic structure for better average hit rate, hash-signature based trace predication is proposed. Based on the above work, a processor-independent co-processor synthesis method is implemented, which can be seamlessly integrated with the hardware and software development process as a system-level design optimization tools. The experiment reveals that the result system performance is increased by 22.6% over instruction trace based method.

• 出版日期2011