Nonphotolithographic nanoscale memory density prospects

作者：DeHon A^*; Goldstein SC; Kuekes PJ; Lincoln P

来源：IEEE Transactions on Nanotechnology, 2005, 4(2): 215-228.

DOI：10.1109/TNANO.2004.837849

• defect tolerance
• electronic nanotechnology
• memory density
• memory organization
• molecular electronics

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The feature's can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization; it is reasonable to expect these technologies to provide memory densities in excess of 10(11) b/cm(2) with modest active power requirements under 0.6 W/Tb/s for random read operations.

• 出版日期2005-3