A low-latency modular switch for CMP systems

作者：Roca Antoni^*; Flich Jose; Silla Federico; Duato Jose

来源：Microprocessors and Microsystems, 2011, 35(8): 742-754.

DOI：10.1016/j.micpro.2011.08.011

• Network-on-chip
• Switch design
• Arbitration implementation

As technology advances, the number of cores in Chip MultiProcessor systems and Multiprocessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies.
In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10% to 21%. Network latency is reduced in a range from 11% to 15%.

• 出版日期2011-11