Fast Linear Model Predictive Control Via Custom Integrated Circuit Architecture

作者：Wills Adrian G^*; Knagge Geoff; Ninness Brett

来源：IEEE Transactions on Control Systems Technology, 2012, 20(1): 59-71.

DOI：10.1109/TCST.2010.2096224

• Field-programmable gate array (FPGA)
• model predictive control (MPC)
• very large scale integration (VLSI)

This paper addresses the implementation of linear model predictive control (MPC) at millisecond range, or faster, sampling rates. This is achieved by designing a custom integrated circuit architecture that is specifically targeted to the MPC problem. As opposed to the more usual approach using a generic serial architecture processor, the design here is implemented using a field-programmable gate array and employs parallelism, pipelining, and specialized numerical formats. The performance of this approach is profiled via the control of a 14th-order resonant structure with 12 sample prediction horizon at 200-mu s sampling rate. The results indicate that no more than 30 mu s are required to compute the control action. A feasibility study indicates that the design can also be implemented in 130 nm CMOS technology, with a core area of 2.5 mm(2). These results illustrate the feasibility of MPC for reasonably complex systems, using relatively cheap, small, and low-power computing hardware.

• 出版日期2012-1