A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-mu m CMOS

作者：Chen Liang Jen; Liu Shen Iuan

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(4): 1470-1483.

DOI：10.1109/TVLSI.2015.2469132

• Linear gain calibration
• time amplifier (TA)
• time domain
• two-step cyclic analog-to-digital converter (ADC)
• voltage-to-time converter (VTC)

Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-mu m CMOS process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a 12-dB gain amplifier, and a time amplifier to achieve a 12-bit resolution. Only linear gain calibration is needed for the TADC. The first TADC achieves a spurious-free dynamic range (SFDR) of 70.5-dB and a signal-to-noise-plus distortion ratio (SNDR) of 64.3 dB. Its power consumption and area are 3 mW and 0.61 mm(2), respectively. The noise analysis for each TADC building block is presented. The calculated results are verified by the transient noise analysis tool in HSPICE. To verify the noise analysis further, a second TADC is fabricated using the VTC with the device size scaled down by a factor of 4 based on the noise analysis. The second TADC achieves an SFDR of 66.8 dB and an SNDR of 59.1 dB. Its power consumption and area are 2.9 mW and 0.61 mm(2), respectively.

• 出版日期2016-4
• 单位中国科学院电工研究所